Motorola MPC823e Reference Manual page 714

Communication Processor Module
16.9.17.2 ACCESSING THE HDLC BUS.The HDLC bus ensures an orderly access to the
bus when two or more transmitters attempt to access it simultaneously. One transmitter is
always successful in completing its transmission. While in the active condition, the HDLC
bus controller monitors the bus using the CTSx pin. It counts the number of one bits using
the CTSx pin and if a zero is detected, the internal counter is cleared. Once eight
consecutive ones have been received, the HDLC bus controller starts transmitting on the
line. While it is transmitting information on the bus, the data is continuously compared with
the CTSx pin and used to sample the external bus. The CTSx sample is taken halfway
through the bit time using the rising edge of the transmit clock. If the transmitted bit is the
same as the received CTSx sample, the HDLC bus controller continues its transmission. If,
however, the received CTSx sample is zero, but the transmitted bit was 1, the HDLC bus
controller stops transmitting after that bit and returns to active condition. Since the HDLC
bus uses a wired-OR scheme, a transmitted zero has priority over a transmitted 1.
Figure 16-84 illustrates how the CTSx pin is used.
TCLK
TXDx
(OUTPUT)
CTSx
(INPUT)
Figure 16-84. Detecting an HDLC Bus Collision
If the source address is included in the HDLC frame and destination address, a predefined
priority of nodes results. Collisions can be detected no later than the end of the source
address, if one is included.
Note: The HDLC bus can be used with many different HDLC-based frame formats.
16-260 MPC823e REFERENCE MANUAL
CTSx SAMPLED AT HALFWAY POINT.
COLLISION DETECTED WHEN
TXD2 IS SET TO 1, BUT CTSx IS SET TO 0.
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