The Bus Monitor - Motorola MPC823e Reference Manual

INTR: • • •
Save state
R3 <- @ SIVEC
R4 <-- Base of branch table
• • •
lbz RX, R3 (0)
add RX, RX, R4
mtspr CTR, RX
bctr
BASE
BASE + 4
BASE + 8
BASE + C
BASE +10
BASE + n
Figure 12-3. Interrupt Table Handling Example

12.4 THE BUS MONITOR

The bus monitor ensures that each bus cycle is terminated within a reasonable period of
time. The MPC823e system interface unit provides a bus monitor option that monitors
internally generated external bus accesses on the external bus. At the start of the transfer
start (TS) signal, the monitor begins counting and stops when the transfer acknowledge (TA)
or transfer error (TEA) signal is asserted. Within the bus cycle, the burst cycle performs
three functions—stops the previous count, resets, and restarts a new count until the next
transfer acknowledge. The last transfer acknowledge of the burst cycle only stops the
counter. When a RETRY signal is asserted, it has the same effect as the TA or TEA signal.
If the monitor times out, a TEA signal is internally asserted by the bus monitor to terminate
the cycle. The programmability of the timeout allows for a variation in system peripheral
response time. The timing mechanism is clocked by the system clock divided by eight. The
maximum value can be 2,040 system clocks. The bus monitor will always be active when
the FRZ signal is asserted or when a debug mode request is pending, regardless of the state
of the BMT bit.
Note: If the bus monitor is disabled, the transfer error conditions will not assert the
TEA pin.
MOTOROLA
INTR: • • •
# load as byte
b Routine1 BASE
b Routine2 BASE + 400
b Routine3
BASE + 800
b Routine4 BASE + C00
•
BASE +1000
•
BASE + n
MPC823e REFERENCE MANUAL
System Interface Unit
Save state
R3 <- @ SIVEC
R4 <-- Base of branch table
• • •
lhz RX, R3 (0) # load as byte
add RX, RX, R4
mtspr CTR, RX
bctr
1st Instruction of Routine1
•
1st Instruction of Routine2
•
1st Instruction of Routine3
•
1st Instruction of Routine4
•
•
•
•
•
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