Motorola MPC823e Reference Manual page 606

Communication Processor Module
16.7.7.2 PROGRAMMING THE GCI INTERFACE. There are two modes of the GCI
interface—normal and SCIT.
16.7.7.2.1 Normal Mode. You can program and configure the channels used for the GCI
bus interface. First, program the SIMODE register to the GCI/SCIT mode for that channel.
This mode defines the sync pulse to GCI sync for framing and data clock as one-half the
input clock rate. You can program more than one channel to interface to the GCI bus. Also,
if the receive and transmit section are used for interfacing the same GCI bus, using the
CRT x bit you must internally connect the receive clock and sync signals to the serial
interface RAM transmit section. Then you must define the GCI frame routing and strobe
select using the serial interface RAM.
When the receive and transmit sections use the same clock and sync signals, these sections
must be programmed to the same configuration. Also, the L1TXD x pin in the I/O register
must be programmed to be an open-drain output. To support the monitor and C/I channels
in GCI, those channels must be routed to one of the serial management controllers. To
support the D channel when there is no possibility of collision, you must clear the GR x bit
corresponding to the serial communication controller that supports the D channel in the
SIMODE register.
16.7.7.2.2 SCIT Mode. To interface with the GCI/SCIT bus, the SIMODE register must be
programmed to GCI/SCIT mode. The serial interface RAM is programmed to support a
96-bit frame length and the frame sync is programmed to the GCI sync pulse. Generally, the
SCIT bus supports the D channel access collision mechanism. For this purpose, you must
program the receive and transmit sections to use the same clock and sync signals with the
CRT x bit and program the GR x bit to transfer the D channel grant to the serial
communication controller that supports this channel. The received bit must be marked by
programming the channel select bits of the serial interface RAM to 111 for an internal
assertion of a strobe on this bit. This bit is sampled by the serial interface and transferred to
the D channel serial communication controller as the grant. The bit is generally bit 4 of the
C/I in channel 2 of GCI, but any other bit can be selected using the serial interface RAM.
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