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System Interface Unit
12.7.3 Real-Time Clock Alarm Seconds Register
The 32-bit real-time clock alarm seconds register (RTSEC) contains the value which divides
the oscillator by 8,192 or 9,600 to generate one clock per second. This register is cleared
when the RTC register is written. Under normal conditions (RTCSC[38K] = 0), PITRTCLK is
assumed to be 8,192 Hz (4.192 MHz/512 or 32.768 KHz/4). RTSEC resets at 8,192 and
increments RTC. Thus, RTC contains the time in seconds and RTSEC functions as a pre-
divider. For a 38.4KHz crystal (instead of 32.768KHz), RTCSC[38K] must be set to make
RTSEC reset at 9,600 instead of 8,192.
RTSEC
BIT
0
1
2
FIELD
RESET
R/W
ADDR
BIT
16
17
18
FIELD
RESET
R/W
ADDR
NOTE: — = Undefined.
COUNTER—Clock Seconds
Counter bits (fraction of a second). Bit 13 is always the LSB of the count. 8,192 = the 38K
field of the RTCSC is set to zero. PITRTCLK is assumed to be 8192Hz (4.192MHz/512 or
32.768KHz/4). 9600 = the 38K field of the RTCSC is set to one. PITRTCLK is assumed to
be 9,600Hz (38.4KHz/4).
Bits 14–31—Reserved
These bits are reserved and must be set to 0.
12-20
3
4
5
6
7
COUNTER
—
R/W
(IMMR & 0xFFFF0000) + 0x228
19
20
21
22
23
RESERVED
—
R/W
(IMMR & 0xFFFF0000) + 0x22A
MPC823e REFERENCE MANUAL
8
9
10
11
12
24
25
26
27
28
13
14
15
RES
—
R/W
29
30
31
MOTOROLA
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