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Memory Controller
• Two User-Programmable Machines
RAM-based machine controls the timing of the external signals with a granularity of
one quarter of a system clock period
User-specified patterns run when a single read access, single write access, burst
read access or burst write access is requested by an internal or external
synchronous master
User-specified patterns run when a single read access or single write access is
requested by an external asynchronous master
UPM periodic timer initiates an automatic pattern when it expires (refresh)
User-specified patterns run under software control
Each UPM can be defined to support DRAM devices with depths of 64K,128K,
256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M, 64M, 128M, and 256M
Four byte-select lines for each UPM
Six external general-purpose lines controlled by each UPM
Supports 8-, 16-, and 32-bit DRAM port sizes
Glueless interface to one bank of DRAM (only external buffers are required for
additional SIMM banks)
Page mode support for successive transfers within a burst for all on-chip and
external synchronous masters
Internal address multiplexing for all on-chip bus masters supporting 64K, 128K,
256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M, 64M, 128M, 256M page banks
Glueless interface to EDO, self refresh, and synchronous DRAM devices
A block diagram of the memory controller is illustrated in Figure 15-1.
15-2
MPC823e REFERENCE MANUAL
MOTOROLA
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