Clocks And Power Control; Features - Motorola MPC823e Reference Manual

SECTION 5

CLOCKS AND POWER CONTROL

The MPC823e clock system provides many different timing options for all on-chip and
external devices. It contains phase-locked loop circuitry and frequency dividers that
generate programmable clock timing for baud rate generators, timers, the LCD controller,
and a variety of low-power mode options.
The programmable phase-locked loop, called the system phase-locked loop (SPLL) in the
MPC823e, generates the overall system operating frequency. You can program the SPLL
in integer multiples of the input clock frequency. The minimum internal operating frequency
is 15MHz. To generate the system operating frequencies, divide by a power of two divider.
The clock sources to the timebase, decrementer, real-time clock, and periodic interrupt
counter are generated by the MPC823e clock module. For additional timer information, refer
to Section 12 System Interface Unit .
The MPC823e has a variety of programmable modes that allow your system to operate at
its highest level, and yet it still gives you the option of operating in a power-saving mode.
Figure 5-1 illustrates the internal clock source and distribution that includes the SPLL, clock
dividers, drivers, and main clock oscillator.

5.1 FEATURES

The following list summarizes the main features of the MPC823e clocks and power control
system:
• Contains System Phase-Locked Loop (SPLL)
• Clock Dividers Are Provided for Low-Power Modes and Internal Clocks
• Contains Five Major Power-Saving Modes:
Normal, Doze, Sleep, Deep Sleep, and Power-Down. Normal and Doze have both
high and low modes of operation.
• Able to Operate the Core at Low Voltage for Various Power-Saving Modes
MOTOROLA MPC823e REFERENCE MANUAL 5-1