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16.6.3.4 IDMA MASK REGISTERS. The 8-bit read/write IDMA1 or 2 mask registers
(IDMRx) have the same bit format as the IDSRx. If a bit in the IDMRx is 1, the corresponding
interrupt in the status register is enabled. If an IDMRx bit is zero, the corresponding interrupt
in the status register is masked.
IDMR1 AND IDMR2
BIT
0
1
FIELD
RESET
R/W
ADDR
Bits 0–4—Reserved
These bits are reserved and must be set to 0.
AD—After Service Buffer Descriptor Done
This status bit is set after servicing a buffer descriptor that has the I bit set.
DONE—IDMA Transfer Done
This bit indicates when the IDMA channel terminates a transfer. It is set after servicing a
buffer descriptor that has the L status bit set.
OB—Out of Buffers
This bit indicates that the IDMA channel has no valid buffer descriptors.
MOTOROLA
2
3
4
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0x914 (IDMR1), 0x91C (IDMR2)
MPC823e REFERENCE MANUAL
Communication Processor Module
5
6
AD
DONE
OB
0
0
R/W
R/W
R/W
7
0
16-95
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