Motorola MPC823e Reference Manual page 585

DSCx—Double Speed Clock for TDMx
This bit controls how some time-division multiplex channels, such as GCI, define the input
clock to be two times faster than the data rate.
0 = The channel clock (L1RCLKx and/or L1TCLKx) is equal to the data clock. Use for
IDL and most TDM formats.
1 = The channel clock rate is twice the data rate. Use for GCI.
CRTx—Common Receive and Transmit Pins for TDMx
This bit is useful when the transmit and receive sections of a given TDM use the same clock
and sync signals. In this mode, the L1TCLKx and L1TSYNCx pins can be used as
general-purpose I/O pins.
0 = Separate pins. The receive section of this TDM uses L1RCLKx and L1RSYNCx
pins for framing and the transmit section uses L1TCLKx and L1TSYNCx for
framing.
1 = Common pins. The receive and transmit sections of this TDM use L1RCLKx as
clock pin of the channel and L1RSYNCx as the receive and transmit sync pin. Use
for IDL and GCI.
STZx—Set L1TXDA to Zero for TDMx
0 = Normal operation.
1 = L1TXDx is set to zero until serial clocks are available, which is useful for GCI
activation.
CEx—Clock Edge for TDMx
0 = Data is transmitted on the rising edge of the clock and received on the falling edge
(use for IDL and GCI).
1 = Data is transmitted on the falling edge of the clock and received on the rising edge.
FEx—Frame Sync Edge for TDMx
This bit indicates when the L1RSYNCx and L1TSYNCx pulses are sampled with the falling
or rising edge of the channel clock.
0 = Falling edge. Use for IDL and GCI.
1 = Rising edge.
GMx—Grant Mode for TDMx
0 = GCI/SCIT mode. The GCI/SCIT D channel grant mechanism for transmission is
internally supported. The grant is one bit from the receive channel. This bit is
marked by programming the channel select bits of the serial interface RAM with
111 to assert an internal strobe on it. See Section 16.7.7.2.2 SCIT Mode.
1 = IDL mode. A grant mechanism is supported if the corresponding GRx bit in the
serial interface clock route register is set. The grant is a sample of the L1GRA pin
while L1TSYNCx is asserted. This grant mechanism implies the IDL access
controls for transmission on the D channel. Refer to
Section 16.7.6.2 Programming the IDL Interface for more information.
MOTOROLA MPC823e REFERENCE MANUAL
Communication Processor Module
16-131