Table of Contents
Advertisement
10.3.3.1 DATA CACHE CONTROL AND STATUS REGISTER. The data cache control
and status register (DC_CST) is used to configure and access the status of the data cache.
DC_CST
BIT
0
1
2
FIELD
DEN
DFWT
LES
RESET
0
0
0
R/W
R
R
R
SPR
BIT
16
17
18
FIELD
RESET
R/W
SPR
NOTE: — = Undefined.
DEN—Data Cache Enable Status
This read-only bit indicates the status of the data cache. Any attempt to write to it is ignored.
You can enable or disable the data cache by writing to the CMD field.
0 = Data cache is disabled.
1 = Data cache is enabled.
DFWT—Data Cache Force Writethrough
This bit is read-only and any attempt to write to it is ignored. Write to the CMD field to set or
force writethrough mode.
0 = Data cache mode is determined by the memory management unit.
1 = Data cache is forced writethrough.
LES—Little-Endian Swap
This bit is read-only. Write to the CMD field to set or clear little-endian swap mode. Refer to
Section 14 Endian Modes for details about using this bit to achieve the required endian
behavior.
0 = Address of the data and the instruction caches is the unchanged address from the
core. No byte swap is done on the data and instruction caches' external accesses.
1 = Address munging performed by the core is reversed before accessing the data
cache, the instruction cache and storage. Byte swap is performed for the
instruction and data caches' external accesses. This bit is a read-only bit and any
attempt to write to it is ignored.
MOTOROLA
3
4
5
6
7
RES
CMD
0
0
R/W
R/W
568
19
20
21
22
23
RESERVED
0
R/W
568
MPC823e REFERENCE MANUAL
8
9
10
11
12
RESERVED
CCER1
CCER2
CCER3
0
0
0
0
R/W
R
R
R
24
25
26
27
28
Data Cache
13
14
15
RESERVED
0
R/W
29
30
31
10-5
Advertisement
Table of Contents
