Motorola MPC823e Reference Manual page 977

If Card B and its socket are configured for I/O interface operation or if the card's power
supply circuitry is using the IRQ signal, CBRDY is:
0 = Card B is requesting an interrupt.
1 = Card B is not requesting an interrupt.
Bits 24–31—Reserved
These bits are reserved and must be set to 0.
17.5.2 PCMCIA Interface Status Change Register
The PCMCIA interface status change register (PSCR) records changes in the state of the
PCMCIA input port signals. This register is reset by writing ones to it (writing zero has no
effect). However, bits 24 and 25 are level-triggered. To clear them, the external source of
the interrupt must be cleared.
PSCR
BIT 0 1 2
FIELD
RESET
R/W
ADDR
BIT 16 17 18
CBVS1 CBVS2 CBWP_ CBCD2
FIELD
_C _C C
RESET
R/W
ADDR
NOTE: — = Undefined.
Bits 0–15—Reserved
These bits are reserved and must be set to 0
CBVS1_C—Card B Voltage Sense 1 Change
0 = Signal is changed.
1 = Signal is unchanged.
CBVS2_C—Card B Voltage Sense 2 Change
0 = Signal is changed.
1 = Signal is unchanged.
MOTOROLA
3 4 5 6 7
RESERVED
—
R/W
(IMMR & 0xFFFF0000) + 0xE8
19 20 21 22 23
CBCD1 CBBVD CBBVD CBRDY
RES
_C _C 2_C 1_C
—
R/W
(IMMR & 0xFFFF0000) + 0xE8
MPC823e REFERENCE MANUAL
PCMCIA Interface
8 9 10 11 12
24 25 26 27 28
CBRDY CBRDY CBRDY
_L _H _R _F
13 14 15
29 30 31
RESERVED
17-11