Motorola MPC823e Reference Manual page 770

Communication Processor Module
16.9.21.12 SCCx TRANSPARENT MASK REGISTER. When a serial communication
controller is in transparent mode, the 16-bit read/write SCCx mask register is referred to as
the SCCx transparent mask (SCCM–Transparent) register. Since each protocol has specific
requirements, the SCCM bits are different for each implementation. It has the same bit
format as the SCCE–Transparent register. If a bit in this register is 1, the corresponding
interrupt in the this register is enabled. If the bit is zero, the corresponding interrupt in this
register is masked.
SCCM–TRANSPARENT
BIT 0 1 2
FIELD RESERVED
RESET 0
R/W R/W
ADDR
16.9.21.13 SCCx TRANSPARENT STATUS REGISTER. When a serial communication
controller is in transparent mode, the 8-bit read-only SCCx status register is referred to as
the SCCx transparent status (SCCS–Transparent) register. Since each protocol has specific
requirements, the SCCS bits are different for each implementation. This register allows you
to monitor real-time status conditions on the RXDx line. The real-time status of the CTSx
and CDx pins are part of the port C parallel I/O.
SCCS–TRANSPARENT
BIT 0
FIELD
RESET
R/W
ADDR
Bits 0–5 and 7—Reserved
These bits are reserved and must be set to 0.
CS—Carrier Sense (DPLL)
This bit shows the real-time internal CSx signal, as determined by the DPLL.
0 = The DPLL does not sense a carrier.
1 = The DPLL senses a carrier.
16-316
3 4 5 6
GLR GLT DCC RES
0 0 0 0
R/W R/W R/W R/W
(IMMR & 0xFFFF0000) + 0xA34
1 2 3
RESERVED
0
R
(IMMR & 0xFFFF0000) + 0xA37
MPC823e REFERENCE MANUAL
7 8 9 10 11
GRA RES TXE RCH BSY
0 0 0
R/W R/W R/W
4 5
12 13 14 15
TX RX
0 0 0 0
R/W R/W R/W R/W
6 7
CS RESERVED
0 0
R R
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