Motorola MPC823e Reference Manual page 452

Memory Controller
CLKOUT/GCLK2
GCLK1
A[6:31]
RD/
WR
D[0:31]
TA
CS2
( )
RAS
[0:3]
BS_B
( [0:3])
CAS
GPL_B1
( )
OE
cst4 Bit 0 1
cst1 Bit 1 1
cst2 Bit 2 0
cst3 Bit 3 0
bst4 Bit 4 0
bst1 Bit 5 0
bst2 Bit 6 0
bst3 Bit 7 0
g0l0 Bit 8
g0l1 Bit 9
g0h0 Bit 10
g0h1 Bit 11
g1t4 Bit 12 1
g1t3 Bit 13 1
g2t4 Bit 14
g2t3 Bit 15
g3t4 Bit 16
g3t3 Bit 17
g4t4 Bit 18
g4t3 Bit 19
g5t4 Bit 20
g5t3 Bit 21
- Bit 22
- Bit 23
loop Bit 24 0
exen Bit 25 0
amx0 Bit 26 0
amx1 Bit 27 0
na Bit 28 0
uta Bit 29 1
todt Bit 30 0
last Bit 31 0
PTS
Figure 15-56. EDO DRAM Refresh Cycle (CAS Before RAS)
15-94
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 1
0 0 0 1
PTS+1 PTS+2 PTS+3 PTS+4
MPC823e REFERENCE MANUAL MOTOROLA