Organization Of The Data Cache - Motorola MPC823e Reference Manual

Data Cache

10.2 ORGANIZATION OF THE DATA CACHE

The data cache is a 8K two-way, set associative, physically addressed cache that has
16-byte line and a 32-bit data path to and from the load/store unit, which allows for a 4-byte
transfer per cycle.
0
20
SET0 TAG0
SET1 TAG1
SET254 TAG254
SET255 TAG255
MMU
COMP
HIT0
10-2
EFFECTIVE ADDRESS
WAY0
. .
W0 W1 W2 W3
W2
. .
W0 W1 W2 W3
. .
W0 W1 W2 W3
. .
W0 W1 W2 W3
20
128
HIT1
HIT
Figure 10-1. Data Cache Organization
MPC823e REFERENCE MANUAL
19 20 21 27
8
WAY1
. .
TAG0 W0 W1 W2 W3
. .
TAG1 W0 W1 W2 W3
L
R
U
A
R
R
A
Y
. .
TAG254 W0 W1 W2 W3
. .
TAG255 W0 W1 W2 W3
20
COMP
BIDIRECTIONAL MUX 2 -> 1
128
TO/FROM LINE BUFFER/
BURST BUFFER
28 31
4
BYTE SELECT
W2
128
MOTOROLA