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Communication Processor Module
16.9.10.2 ASYNCHRONOUS PROTOCOLS. In asynchronous protocols, the RTSx pin is
asserted when SCCx data is loaded into the transmit FIFO and a falling transmit clock
occurs. The CDx and CTSx pins can be used to control reception and transmission in the
same manner as the synchronous protocols. The first bit of data transmission in an
asynchronous protocol is the start bit of the first character. In addition, the UART protocol
has an option for CTSx flow control as described in Section 16.9.15 The SCCs in UART
Mode.
If CTSx is already asserted when RTSx is asserted, transmission begins in two additional
bit times. However, if CTSx is not already asserted when RTSx is asserted and the CTSS
bit is set to 0 in the GSMR_H, then transmission begins in three additional bit times. If CTSx
is not already asserted when RTSx is asserted and CTSS is set to 1, then transmission
begins in two additional bit times.
16.9.11 Digital Phase-Locked Loop Operation
Each SCCx channel includes a digital phase-locked loop (DPLL) that is used to recover
clock information from a received datastream. For applications that provide a direct clock
source to the serial communication controllers, the DPLL can be bypassed if it is
programmed to do so in the GSMR_L. The DPLL must not be used when a serial
communication controller is programmed to Ethernet and it is optional for other protocols.
The DPLL receiver block diagram is illustrated in Figure 16-70 and the transmitter block
diagram is illustrated in Figure 16-71.
The DPLL can be driven by an external clock or one of the baud rate generator outputs and
they must be approximately 8x, 16x, or 32x the data rate, depending on the encoding or
decoding preferred. The DPLL uses this clock, along with the datastream, to construct a
data clock that can be used as the SCC2 receive and/or transmit clock. In all modes, the
DPLL uses the input clock to determine the nominal bit time.
At the beginning of operation, the DPLL is in search mode, whereas the first transition resets
the internal DPLL counter and begins DPLL operation. While the counter is counting, the
DPLL monitors the incoming datastream for transitions and when a transition is detected,
the DPLL makes a count adjustment to produce an output clock that tracks the incoming
bits.
MOTOROLA
MPC823e REFERENCE MANUAL
16-193
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