Motorola MPC823e Reference Manual page 958

SCCE
EVENT
BIT
SCCM
MASK
BIT
Figure 16-136. Interrupt Request Masking
16.15.4 Generating and Calculating an Interrupt Vector
All pending unmasked CPM interrupts are presented to the core in order of priority. The core
responds to an interrupt request by setting the IACK bit in the CIVR. The interrupt vector that
allows the core to locate the interrupt service routine is made available to the core by reading
the CIVR. For CPM interrupts, the CPM interrupt controller passes an interrupt vector
corresponding to the unmasked pending interrupt of the highest priority. The CPM interrupt
controller encoding of the five low-order bits of the interrupt vector is shown in Table 16-46.
MOTOROLA
CIPR
13 INPUT
OR
(13 EVENT BITS)
CIMR
MASK
BIT
MPC823e REFERENCE MANUAL
Communication Processor Module
REQUEST
TO THE IMB
AT THE
LEVEL
SPECIFIED
28 INPUT
IN IRL2–IRL0
OR
IN THE CICR.
(28 CIPR BITS)
16-504