Motorola MPC823e Reference Manual page 450

Memory Controller
CLKOUT/GCLK2
GCLK1
A[6:31]
ROW COLUMN 1
RD/
WR
D[0:31]
TA
CS2
( )
RAS
[0:3]
BS_B
( [0:3])
CAS
GPL_B1
( )
OE
cst4 Bit 0 0 0
cst1 Bit 1 0 0
cst2 Bit 2 0 0
cst3 Bit 3 0 0
bst4 Bit 4 1 1
bst1 Bit 5 1 0
bst2 Bit 6 1 0
bst3 Bit 7 1 0
g0l0 Bit 8
g0l1 Bit 9
g0h0 Bit 10
g0h1 Bit 11
g1t4 Bit 12 0 0
g1t3 Bit 13 0 0
g2t4 Bit 14
g2t3 Bit 15
g3t4 Bit 16
g3t3 Bit 17
g4t4 Bit 18
g4t3 Bit 19
g5t4 Bit 20
g5t3 Bit 21
- Bit 22
- Bit 23
loop Bit 24 0 0
exen Bit 25 0 0
amx0 Bit 26 0 0
amx1 Bit 27 0 0
na Bit 28 0 0
uta Bit 29 1 1
todt Bit 30 0 0
last Bit 31 0 0
RBS RBS+1 RBS+2 RBS+3 RBS+4
Figure 15-54. EDO DRAM Burst Read Access
15-92
COLUMN 2
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 0 1
0 1 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 1 0 1
0 0 0 0
0 0 0 0
1 0 0 1
1 0 1 0
0 0 0 0
0 0 0 0
RBS+5
MPC823e REFERENCE MANUAL
COLUMN 3 COLUMN 4
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 0 1 0
1 0 1 0
0 1 0 1
0 1 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 1 0 0
0 0 0 0
0 0 0 0
0 1 0 0
1 0 1 0
0 0 0 0
0 0 0 0
RBS+6 RBS+7 RBS+8 RBS+9 RBS+10
0
0
1
1
1
1
1
1
0
1
0
0
1
0
0
1
1
1
MOTOROLA