Motorola MPC823e Reference Manual page 586

Communication Processor Module
TFSDx—Transmit Frame Sync Delay for TDMx
This field determines the number of clock delays between the transmit sync and the first bit
of the transmit frame.
00 = No bit delay. The first bit of the frame is transmitted/received on the same clock
as the sync.
01 = 1-bit delay.
10 = 2-bit delay.
11 = 3-bit delay.
L1CLKx
(CE=0)
L1SYNCx
(FE=1)
DATA
ONE CLOCK DELAY FROM SYNC LATCH TO FIRST BIT OF FRAME
Figure 16-52. Example of One Clock Delay from Sync to Data (RFSDx = 01)
L1CLKx
(CE=0)
L1SYNCx
(FE=1)
DATA
NO DELAY FROM SYNC LATCH TO FIRST BIT OF FRAME
Figure 16-53. Example of No Delay from Sync to Data (RFSDx = 00)
16-132
BIT 0 BIT 1 BIT 2 BIT 3
BIT 0 BIT 1 BIT 2 BIT 3
MPC823e REFERENCE MANUAL
END OF FRAME
BIT 4
BIT 4 BIT 0 BIT 1
BIT 0
BIT 2
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