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4.1.2 External Hard Reset
HRESET (hard reset) is a bidirectional, active low I/O pin. The MPC823e can only detect an
external assertion of HRESET if it occurs while the MPC823e is not asserting reset. During
HRESET, SRESET is asserted. HRESET is an open-collector type of pin. SRESET (soft
reset) is a bidirectional, active low I/O pin. The MPC823e can only detect an external
assertion of SRESET if it occurs while the MPC823e is not asserting reset. The SRESET is
also an open-collector type of pin.
When an external HRESET is asserted, the core starts driving the HRESET and SRESET
for 512 cycles. When the timer expires, after 512 cycles, the configuration is sampled from
the data pins and the core stops driving the HRESET and SRESET pins. An external pull-up
resistor should drive the pins high and once they are negated, a 16-cycle period passes
before the presence of an external (hard/soft) reset is tested. Refer to Section 4.3.1 Hard
Reset for more information.
4.1.3 Internal Hard Reset
When the core finds a reason to assert HRESET, it starts driving the HRESET and SRESET
pins for 512 cycles. When the timer expires, after the 512 cycles, the configuration is
sampled from data pins and the core stops driving the pins. An external pull-up resistor
should drive the HRESET and SRESET pins high and once they are negated a 16-cycle
period passes before the presence of an external (hard/soft) reset is tested. Refer to
Section 4.3.1 Hard Reset for more information. The causes of internal hard reset are as
follows:
• Loss of lock
• Software watchdog reset
• Checkstop reset
• Debug port hard reset
• JTAG reset
4.1.3.1 LOSS OF LOCK. If the PLL detects a loss of lock, erroneous external bus operation
occurs if synchronous external devices use the core input clock. Erroneous operation could
also occur if devices with a PLL use the core clockout. This source of reset can be asserted
if the LOLRE bit in the PLL low-power and reset control register is set. The enabled PLL
loss-of-lock event generates an internal hard reset sequence.
4.1.3.2 SOFTWARE WATCHDOG RESET. After the core watchdog counts to zero, a
software watchdog reset is asserted. The enabled software watchdog event then generates
an internal hard reset sequence.
4.1.3.3 CHECKSTOP RESET. If the core enters a checkstop state and the checkstop reset
is enabled, the checkstop reset is asserted. The enabled checkstop event then generates
an internal hard reset sequence.
MOTOROLA
MPC823e REFERENCE MANUAL
Reset
4-3
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