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Memory Management Unit
Each TLB entry holds an access protection group (APG) number. When a match is detected,
the value of the matched entry's APG is used to index a field in the access protection register
that defines access control for the translation. The access protection register contains 16
fields. The field content is used according to the group protection mode. In the PowerPC
mode, each field holds the Kp and Ks bits of a corresponding segment register. To be
consistent with the PowerPC Microprocessor Family: The Programming Environment for
32-Bit Microprocessors manual, the APG value must match the four most-significant bits of
the effective page number. In domain manager mode, each field holds override information
over the page protection setting. No override, no access override, and free access override
modes are all supported.
11.4 STORAGE CONTROL
The memory management unit can be used to map a block of memory in different access
modes. Each page can have different storage control attributes. The MPC823e supports
cache inhibit, writethrough, and guarded attributes, but not the memory coherence attribute.
A page that needs to be memory coherent must be programmed cache-inhibited. Refer to
the definition of these attributes in the PowerPC Microprocessor Family: The Programming
Environment for 32-Bit Microprocessors manual. The effects of the cache-inhibit and
writethrough attributes in the MPC823e are described in Section 9 Instruction Cache .
The guarded attribute is used to map I/O devices that are sensitive to speculative accesses.
An attempt to access a page marked guarded with the guarded bit asserted forces the
access to stall until the access is nonspeculative or canceled by the core. Fetching from a
guarded storage is prohibited and if it is attempted an implementation-specific instruction
storage interrupt is generated. When MSR
or MSR
for instruction or data address
IR
DR
translation are negated, default attributes are used. See Section 11.6.1.1 MMU Instruction
Control Register and Section 11.6.1.2 MMU Data Control Register for details.
The MPC823e does not generate an exception for a reference bit update because there is
no entry for a reference bit in the translation lookaside buffer. The change bit updates are
implemented by the software, but the hardware treats the change bit as a write-protect
attribute. Therefore, if you try to write to a page marked unmodified, that entry is invalidated
and an implementation-specific data TLB error interrupt is generated.
11-4
MPC823e REFERENCE MANUAL
MOTOROLA
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