Motorola MPC823e Reference Manual page 690

Communication Processor Module
Note: The SCCx HDLC controller must receive a maximum of eight clocks (after a
frame is received) to complete the reception.
16.9.16.4 SCCx HDLC PARAMETER RAM MEMORY MAP.When configured to operate
in HDLC mode, the serial communication controllers overlay the structure used in Table 16-
24 with the HDLC parameters that are described in Table 16-27 below.
Table 16-27. SCCx HDLC Parameter RAM Memory Map
ADDRESS
SCCx Base + 30
SCCx Base + 34
SCCx Base + 38
SCCx Base + 3C
SCCx Base + 3E
SCCx Base + 40
SCCx Base + 42
SCCx Base + 44
SCCx Base + 46
SCCx Base + 48
SCCx Base + 4A
SCCx Base + 4C
SCCx Base + 4E
SCCx Base + 50
SCCx Base + 52
SCCx Base + 54
SCCx Base + 56
SCCx Base + 58
SCCx Base + 5A
NOTE: You are only responsible for initializing the items in bold.
SCCx base = (IMMR & 0xFFFF0000) + 0x3D00 (SCC2) and 0x3E00 (SCC3).
All references to registers in the parameter RAM table are actually implemented in the dual-port RAM
area as a memory-based register.
16-236
NAME WIDTH
RES Word
C_MASK Word
C_PRES Word
DISFC Half-word
CRCEC Half-word
ABTSC Half-word
NMARC Half-word
RETRC Half-word
MFLR Half-word
MAX_CNT Half-word
RFTHR Half-word
RFCNT Half-word
HMASK Half-word
HADDR1 Half-word
HADDR2 Half-word
HADDR3 Half-word
HADDR4 Half-word
TMP Half-word
TMP_MB Half-word
MPC823e REFERENCE MANUAL
DESCRIPTION
Reserved
CRC Constant
CRC Preset
Discard Frame Counter
CRC Error Counter
Abort Sequence Counter
Nonmatching Address RX Counter
Frame Transmission Counter
Max Frame Length Register
Maximum Length Counter
Received Frames Threshold
Received Frames Count
User-Defined Frame Address Mask
User-Defined Frame Address
User-Defined Frame Address
User-Defined Frame Address
User-Defined Frame Address
Temp Storage
Temp Storage
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