Motorola MPC823e Reference Manual page 371

ACS—Address to Chip-Select Setup/G5LA
This field is used for the GPCM and the G5LA and G5LS fields are used for the UPM. This
field controls CSx signal assertion in relation to address lines valid.
00 = CSx is output at the same time as the address lines.
01 = Reserved.
10 = CSx is output a quarter of a clock later than the address lines.
11 = CSx is output half a clock later than the address lines.
G5LS—General-Purpose Line 5 A
This field determines how the internal timing generator (GPL5) signal is output when the
memory access is handled by the UPMA or UPMB.
G5LA (only valid for UPMB):
0 = Output the internal GPL5 signal on the GPL_B5 pin.
1 = Output the internal GPL5 signal on the GPL_A5 pin.
G5LS (valid for UPMA or UPMB):
0 = The GPL5 signal is driven low on the falling edge of GCLK1 during the first clock
cycle of a read or write memory access.
1 = The GPL5 signal is driven high on the falling edge of GCLK1 during the first clock
cycle of a read or write memory access.
BIH—Burst Inhibit
This bit determines whether or not this memory bank supports burst accesses. When a burst
does not occur, the memory controller drives the BI signal active when accessing this
memory region. If the machine selected to handle this access is the GPCM, this bit must be
set to 1.
0 = The BI signal is negated. The bank supports burst accesses.
1 = The BI signal is asserted. The bank does not support burst accesses.
SCY—Select Cycle Length (GPCM only)
This field determines the number of wait states inserted in the cycle when the
general-purpose chip-select machine handles the external memory access. It is one of the
parameters that control the cycle's length. The total cycle length is controlled by this
parameter and the TRLX field. Refer to Table 15-2 (page 15-28) for the total number of
cycles.
MOTOROLA MPC823e REFERENCE MANUAL
Memory Controller
15-13