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EXTC—External Clock Source
This field selects the baud rate generator input clock from the internal BRGCLK or one of
three external pins.
00 = The baud rate generator input clock comes from the BRGCLK (internal clock
generated by the clock synthesizer in the system interface unit).
01 = The baud rate generator input clock comes from the CLK2 pin.
10 = The baud rate generator input clock comes from the CLK4 pin.
11 = Reserved.
ATB—Autobaud
When set, this bit selects autobaud operation of the baud rate generator on the
corresponding RXDx pin.
0 = Normal operation of the baud rate generator.
1 = When RXDx goes low, the baud rate generator determines the length of the start
bit and synchronizes the baud rate generator to the actual baud rate.
Note: The ATB bit must remain clear (0) until the serial communication controller
receives the three RX clocks. Then you must set this bit to one to obtain the
correct baud rate. Once the baud rate is obtained and locked, it is indicated by
setting the AB bit in the SCCE-UART register in Section 16.9.15.18 SCCx
UART Event Register. This bit may only be set for BRG2.
CD—Clock Divider
This field and the prescaler determines the baud rate generator output clock rate. They are
used to preset a 12-bit counter that is decremented at the prescaler output rate, but the
counter is inaccessible to you. When the counter reaches zero, it is reloaded from the clock
divider bits. Thus, a value of 0xFFF in CD0–CD11 produces the minimum clock rate (divide
by 4,096), and a value of 0x0000 produces the maximum clock rate (divide by 1). Even when
dividing by an odd number, the counter ensures a 50% duty-cycle by asserting the terminal
count once on clock low and next on clock high. The terminal count signals counter
expiration and toggles the clock.
DIV16—BRG Clock Prescaler Divide by 16
0 = Divide by 1 for the clock divider input.
1 = Divide-by-16 prescaler enabled for the clock divider output.
MOTOROLA
MPC823e REFERENCE MANUAL
Communication Processor Module
16-161
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