External Bus Interface
CLKOUT
BR
BG
BB
A[6:31]
RD/WR
TSIZ[0:1],AT[0:3]
BURST
TS
DATA
TA
Figure 13-8. Single Beat Write Cycle of One Wait State
13-14
RECEIVE BUS GRANT AND BUS BUSY NEGATED
ASSERT BB, DRIVE ADDRESS AND ASSERT TS
WAIT STATE
MPC823e REFERENCE MANUAL
DATA IS SAMPLED
MOTOROLA