Motorola MPC823e Reference Manual page 768

Communication Processor Module
UN—Underrun
This bit indicates that a serial communication controller has encountered a transmitter
underrun condition while transmitting the associated data buffer.
CT—CTS Lost
This bit indicates the CTSx signal has been lost during frame transmission.
DATA LENGTH
This field represents the number of bytes that the communication processor module must
transmit from this buffer descriptor data buffer. It must be greater than zero, even or odd.
This value is never modified by the communication processor module.
TX DATA BUFFER POINTER
This field always points to the first byte of the associated data buffer. It can be even or odd,
and can reside in internal or external memory.
16.9.21.11 SCCx TRANSPARENT EVENT REGISTER. When a serial communication
controller is in transparent mode, the 16-bit, memory-mapped SCCx event register is
referred to as the SCCx transparent event register (SCCE–Transparent). Since each
protocol has specific requirements, the SCCE bits are different for each implementation.
This register is used to report events recognized by the transparent channel and to generate
interrupts. When an event is recognized, the SCCx Transparent controller sets the
corresponding bit in this register. Interrupts generated by this register can be masked in the
SCCM–Transparent register.
A bit is reset by writing a 1 (writing a zero has no effect) and more than one bit can be reset
at a time. All unmasked bits must be reset before the communication processor module
negates the internal interrupt request signal. This register is cleared at reset and can be read
at any time.
SCCE–TRANSPARENT
BIT 0 1 2
FIELD RESERVED
RESET 0
R/W R/W
ADDR
Bits 0–2, 6–7, and 9–10—Reserved
These bits are reserved and must be set to 0.
GLR—Glitch on RX
If set, this bit indicates that a serial communication controller has found a glitch on the
receive clock.
16-314
3 4 5 6
GLR GLT DCC RES
0 0 0 0
R/W R/W R/W R/W
(IMMR & 0xFFFF0000) + 0xA30
MPC823e REFERENCE MANUAL
7 8 9 10 11
GRA RES TXE RCH BSY
0 0 0
R/W R/W R/W
12 13 14 15
TX RX
0 0 0 0
R/W R/W R/W R/W
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