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Memory Controller
CLKOUT
A[6:27]
A[28:31]
RD/
WR
TSIZEx
AS
TA
CSx
WEx
OE
DATA
Figure 15-36. Asynchronous External Master Access
To connect to external memory devices that require address multiplexing, use the GPL_x5
pin. The state of the GPL_x5 signal logic value depends on the configuration defined in
Table 15-9. The GPL_x5 pin reflects the value of the G5LS bit of the corresponding option
register in the first clock cycle of the slave device access. In subsequent clock cycles, the
state of GPL_x5 is determined by the G5T4 and G5T3 bits in the RAM word. If the UPMB
controls the slave access, you can use the G5LA bit of the option register to select the active
GPL_x5 signal. G5LS only applies to memory requests and not RAM words executed by
internal/external software, exception, or memory periodic timer requests.
15-70
ADDRESS
MATCH
AND
COMPARE
MPC823e REFERENCE MANUAL
MEMORY
DEVICE
ACCESS
MOTOROLA
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