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System Interface Unit
TBREFL
BIT
0
1
2
FIELD
RESET
R/W
ADDR
BIT
16
17
18
FIELD
RESET
R/W
ADDR
NOTE: — = Undefined.
TBREFL—Timebase Reference Lower
These bits represent the 32-bit reference value for the lower part of the timebase.
12.6.3 Timebase Status and Control Register
The 16-bit read/write timebase status and control register (TBSCR) controls the timebase
count enable and interrupt generation. It is also is used for reporting the source of the
interrupts and can be read at any time. A status bit is cleared by writing a 1 (writing a zero
has no effect) and more than one bit can be cleared at a time.
TBSCR
BIT
0
1
2
FIELD
RESET
R/W
ADDR
TBIRQ—Timebase Interrupt Request
This field determines the interrupt priority level of the timebase. To specify a certain level,
the appropriate bit must be set.
REFA and REFB—Reference Interrupt Status
If set, these bits indicate that a match has been detected between the corresponding
reference register (TBREFU for REFA and TBREFL for REFB) and the timebase low
register. Each bit must be cleared by writing a 1.
12-16
3
4
5
6
7
TBREFL
—
R/W
(IMMR & 0xFFFF0000) + 0x208
19
20
21
22
23
TBREFL
—
R/W
(IMMR & 0xFFFF0000) + 0x20A
3
4
5
6
7
TBIRQ
0
R/W
(IMMR & 0xFFFF0000) + 0x200
MPC823e REFERENCE MANUAL
8
9
10
11
12
24
25
26
27
28
8
9
10
11
12
REFA
REFB
RESERVED
REFAE
0
0
0
0
R/W
R/W
R/W
R/W
13
14
15
29
30
31
13
14
15
REFBE
TBF
TBE
0
0
0
R/W
R/W
R/W
MOTOROLA
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