Motorola MPC823e Reference Manual page 887

16.11.8.6 SMCx GCI MASK REGISTER. When a serial management controller is in GCI
mode, the 8-bit, memory-mapped, read/write SMCx mask register is referred to as the SMCx
GCI mask (SMCM–GCI) register. It has the same bit format as the SMCE–GCI register. If a
bit in this register is a 1, the corresponding interrupt in the SMCE–GCI is enabled. If the bit
is zero, the corresponding interrupt in the SMCE–GCI is masked.
SMCM–GCI
BIT 0 1
FIELD
RESET
R/W
ADDR
16.12 THE SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI) allows the MPC823e to exchange data between other
MPC8xx microprocessors, the MC68328, MC68360, and MC68302 embedded
microprocessors, as well as the MC68HC11 and MC68HC05 microcontroller families and a
variety of peripheral devices.
The serial peripheral interface is a full-duplex, synchronous, character-oriented channel that
supports a four-wire interface (receive, transmit, clock and slave select). The SPI block
consists of transmitter and receiver sections, an independent baud rate generator, and a
control unit. The transmitter and receiver sections use the same clock, which is derived from
the SPI baud rate generator in master mode and generated externally in slave mode. During
an SPI transfer, data is transmitted and received simultaneously.
Because the SPI receiver and transmitter are double-buffered, as illustrated in the block
diagram below, the effective FIFO size is 2 characters. You can program the MPC823e
serial peripheral interface to shift out the most- or least-significant bit first. When the serial
peripheral interface is not enabled in the SPMODE register, it consumes very little power.
MOTOROLA
2 3
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0xA8A (SMC1), 0xA9A(SMC2)
MPC823e REFERENCE MANUAL
Communication Processor Module
4 5 6
CTXB CRXB MTXB
0 0 0
R/W R/W R/W
7
MRXB
0
R/W
16-433