Floating-Point Status/Control Register (Fpscr) - Hitachi SH7750 Programming Manual

6.3.2

Floating-Point Status/Control Register (FPSCR)

Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001)
• FR: Floating-point register bank
FR = 0: FPR0_BANK0–FPR15_BANK0 are assigned to FR0–FR15; FPR0_BANK1–
FPR15_BANK1 are assigned to XF0–XF15.
FR = 1: FPR0_BANK0–FPR15_BANK0 are assigned to XF0–XF15; FPR0_BANK1–
FPR15_BANK1 are assigned to FR0–FR15.
• SZ: Transfer size mode
SZ = 0: The data size of the FMOV instruction is 32 bits.
SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits).
• PR: Precision mode
PR = 0: Floating-point instructions are executed as single-precision operations.
PR = 1: Floating-point instructions are executed as double-precision operations (graphics
support instructions are undefined).
Do not set SZ and PR to 1 simultaneously; this setting is reserved.
[SZ, PR = 11]: Reserved (FPU operation instruction is undefined.)
• DN: Denormalization mode
DN = 0: A denormalized number is treated as such.
DN = 1: A denormalized number is treated as zero.
Cause FPU exception
cause field
Enable FPU exception
enable field
Flag FPU exception
flag field
When an FPU exception is requested, the corresponding bits in the cause and flag fields are set
to 1. Each time an FPU operation instruction is executed, the cause field is cleared to 0 first.
The flag field retains the value of 1 until cleared to 0 by software.
FPU Invalid
Error (E) Operation (V)
Bit 17 Bit 16
None Bit 11
None Bit 6
Division Overflow
by Zero (Z) (O)
Bit 15 Bit 14
Bit 10 Bit 9
Bit 5 Bit 4
Rev. 2.0, 03/99, page 123 of 396
Underflow Inexact
(U) (I)
Bit 13 Bit 12
Bit 8 Bit 7
Bit 3 Bit 2