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13.2.9
Refresh Timer Control/Status Register (RTSCR)
The refresh timer control/status register (RTSCR) is a 16-bit readable/writable register that
specifies the refresh cycle and whether interrupts are to be generated.
RTSCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Bits 15 to 8—Reserved: These bits are always read as 0. For the write values, see section 13.2.13,
Notes on Accessing Refresh Control Registers.
Bit 7—Compare-Match Flag (CMF): Status flag that indicates a match between the refresh
timer counter (RTCNT) and refresh time constant register (RTCOR) values.
Bit 7: CMF
0
1
Note: * If 1 is written, the original value is retained.
Bit 6—Compare-Match Interrupt Enable (CMIE): Controls generation or suppression of an
interrupt request when the CMF flag is set to 1 in RTCSR. Do not set this bit to 1 when CAS-
before-RAS refreshing or auto-refreshing is used.
Bit 6: CMIE
0
1
Rev. 4.0, 04/00, page 304 of 850
15
14
—
—
0
0
—
—
7
6
CMF
CMIE
0
0
R/W
R/W
Description
RTCNT and RTCOR values do not match
[Clearing condition]
When 0 is written to CMF
RTCNT and RTCOR values match
[Setting condition]
When RTCNT = RTCOR*
Description
Interrupt requests initiated by CMF are disabled
Interrupt requests initiated by CMF are enabled
13
12
—
—
0
0
—
—
5
4
CKS2
CKS1
0
0
R/W
R/W
11
10
—
—
0
0
—
—
3
2
CKS0
OVF
0
0
R/W
R/W
9
8
—
—
0
0
—
—
1
0
OVIE
LMTS
0
0
R/W
R/W
(Initial value)
(Initial value)
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