Peripheral Module Pin Pull-Up Control; Standby Control Register 2 (Stbcr2) - Hitachi SH7750 Programming Manual

9.2.3

Peripheral Module Pin Pull-Up Control

When bit 5 in the standby control register (STBCR) is cleared to 0, peripheral module related pins
are pulled up when in the input or high-impedance state.
• Relevant Pins
SCI related pins
DMA related pins
TMU related pin
9.2.4

Standby Control Register 2 (STBCR2)

Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep
mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via
the pin or due to watchdog timer overflow.
Bit:
Initial value:
R/W:
Bit 7—Deep Sleep (DSLP): Specifies a transition to deep sleep mode
Bit 7: DSLP
0
1
Note: * When the STBY bit in the STBCR register is 0
Bits 6 to 0—Reserved: Only 0 should only be written to these bits; operation cannot be
guaranteed if 1 is written. These bits are always read as 0.
Rev. 2.0, 03/99, page 182 of 396
MD0/SCK
MD7/TXD
RXD
TCLK
7 6
DSLP —
0 0
R/W R
Description
Transition to sleep mode or standby mode on execution of SLEEP
instruction, according to setting of STBY bit in STBCR register (Initial value)
Transition to deep sleep mode on execution of SLEEP instruction*
MD1/TXD2
MD8/RTS2
CTS2
DACK0
DACK1
5 4 3
— — —
0 0 0
R R R
MD2/RXD2
SCK2/
DRAK0
DRAK1
2 1 0
— — —
0 0 0
R R R