Standby Control Register 2 (Stbcr2) - Hitachi SH7751 Hardware Manual

9.2.4

Standby Control Register 2 (STBCR2)

Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep
mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via


the pin or due to watchdog timer overflow.
Bit: 7
DSLP
Initial value: 0
R/W: R/W
Bit 7—Deep Sleep (DSLP): Specifies a transition to deep sleep mode
Bit 7: DSLP
0
1
Note: * When the STBY bit in the STBCR register is 0
Bit 6—STATUS Pin High-Impedance Control (STHZ): This bit selects whether the STATUS0
and 1 pins are set to high-impedance when in hardware standby mode.
Bit 6: STHZ
0
1
Bits 5 to 2—Reserved: Only 0 should only be written to these bits; operation cannot be
guaranteed if 1 is written. These bits are always read as 0.
Bit 1—Module Stop 6 (MSTP6): Specifies that the clock supply to the store queue (SQ) in the
cache controller (CCN) is stopped. Setting the MSTP6 bit to 1 stops the clock supply to the SQ,
and the SQ functions are therefore unavailable.
Bit 1: MSTP6
0
1
6 5
STHZ —
0 0
R/W R
Description
Transition to sleep mode or standby mode on execution of SLEEP
instruction, according to setting of STBY bit in STBCR register (Initial value)
Transition to deep sleep mode on execution of SLEEP instruction*
Description
Sets STATUS0, 1 pins to high-impedance when in hardware standby mode
Drives STATUS0, 1 pins to LH when in hardware standby mode
Description
SQ operating
Clock supply to SQ stopped
4 3
— —
0 0
R R
Rev. 3.0, 04/02, page 221 of 1064
2 1
— MSTP6 MSTP5
0 0
R R/W R/W
(Initial value)
(Initial value)
0
0