Operand Cache (Oc); Configuration - Hitachi SH7750 series Hardware Manual

4.3

Operand Cache (OC)

4.3.1

Configuration

Figure 4.2 shows the configuration of the operand cache.
Effective address
31 26 25
OIX
22
MMU
19
RAM area
determination
ORA
[13]
9
Address array
Tag
0
511 19 bits
Compare
Hit signal
Figure 4.2 Configuration of Operand Cache
13 12 11 10 9
[12]
Longword (LW) selection
3
U V LW0 LW1
1 bit 1 bit 32 bits 32 bits
5 4 3 2 1
[11:5]
Data array
LW2 LW3 LW4
32 bits 32 bits 32 bits 32 bits
Read data
Rev. 4.0, 04/00, page 65 of 850
0
LW5 LW6 LW7
32 bits 32 bits
Write data