Operand Cache (Oc); Configuration - Hitachi SH7750 Programming Manual

4.3

Operand Cache (OC)

4.3.1

Configuration

Figure 4.2 shows the configuration of the operand cache.
Effective address
31 26 25
OIX
22
9
MMU
19
RAM area
determination
ORA
[13]
Address array
Tag address U
0
511 19 bits 1 bit 1 bit
Compare
Hit signal
Figure 4.2 Configuration of Operand Cache
13 12 11 10 9
[11:5]
[12]
Longword (LW) selection
3
V
LW0 LW1 LW2
32 bits 32 bits 32 bits
Read data
5 4 3 2 1 0
Data array
LW3 LW4 LW5 LW6
32 bits 32 bits 32 bits 32 bits
Write data
Rev. 2.0, 03/99, page 65 of 396
LW7
32 bits