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Reset and clock control (RCC) for STM32F413/423
6.3.18
RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) for STM32F413xx
Address offset: 0x54
Reset value: 0x0000 00C0
Access: no wait state, word, half-word and byte access.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode
Bit 6 RNGLPEN: RNG clock enable during Sleep mode
Bits 5:0 Reserved, must be kept at reset value.
162/1324
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Set and cleared by software.
0: USB OTG FS clock disabled during Sleep mode
1: USB OTG FS clock enabled during Sleep mode
Set and cleared by software.
0: RNG clock disabled during Sleep mode
1: RNG clock enabled during Sleep mode
24
23
22
Res.
Res.
Res.
Res.
8
7
6
OTGFS
RNG
Res.
Res.
LPEN
LPEN
rw
rw
RM0430 Rev 8
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
RM0430
17
16
Res.
Res.
1
0
Res.
Res.
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