Rcc Ahb2 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb2Lpenr) - ST STM32F446 Series Reference Manual

RM0390
Bit 6 GPIOGLPEN: IO port G clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port G clock disabled during Sleep mode
1: IO port G clock enabled during Sleep mode
Bit 5 GPIOFLPEN: IO port F clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port F clock disabled during Sleep mode
1: IO port F clock enabled during Sleep mode
Bit 4 GPIOELPEN: IO port E clock enable during Sleep mode
Set and cleared by software.
0: IO port E clock disabled during Sleep mode
1: IO port E clock enabled during Sleep mode
Bit 3 GPIODLPEN: IO port D clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port D clock disabled during Sleep mode
1: IO port D clock enabled during Sleep mode
Bit 2 GPIOCLPEN: IO port C clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port C clock disabled during Sleep mode
1: IO port C clock enabled during Sleep mode
Bit 1 GPIOBLPEN: IO port B clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port B clock disabled during Sleep mode
1: IO port B clock enabled during Sleep mode
Bit 0 GPIOALPEN: IO port A clock enable during sleep mode
This bit is set and cleared by software.
0: IO port A clock disabled during Sleep mode
1: IO port A clock enabled during Sleep mode
6.3.16 RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR)
Address offset: 0x54
Reset value: 0x0000 0081
Access: no wait state, word, half-word and byte access.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
OTGFS
Res. Res.
LPEN
rw
RM0390 Rev 4
Reset and clock control (RCC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
17 16
Res. Res.
1 0
DCMI
Res.
LPEN
rw
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