Table 13. Description Of The Option Bytes - STMicroelectronics RM0365 Reference Manual

Option byte description
Flash memory
address
0x1FFF F800
0x1FFF F804
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Table 13. Description of the option bytes

Bits [31:24]: nUSER
Bits [23:16]: USER: User option byte (stored in FLASH_OBR[15:8])
This byte is used to configure the following features:
- Select the watchdog event: Hardware or software
- Reset event when entering Stop mode
- Reset event when entering Standby mode
Bit 23: Reserved
Bit 22: SRAM_PE (not available in STM32F302x6/8 devices)
The SRAM hardware parity check is disabled by default. This bit allows the user to
enable the SRAM hardware parity check.
0: Parity check enabled.
1: Parity check disabled.
Bit 21: VDDA_MONITOR
This bit selects the analog monitoring on the VDDA power source:
0: VDDA power supply supervisor disabled.
1: VDDA power supply supervisor enabled.
Bit 20: nBOOT1
Together with the BOOT0 pin, this bit selects Boot mode from the main Flash
memory, SRAM or System memory. Refer to
Bit 19: Reserved, must be kept at reset.
Bit 18: nRST_STDBY
0: Reset generated when entering Standby mode.
1: No reset generated.
Bit 17: nRST_STOP
0: Reset generated when entering Stop mode
1: No reset generated
Bit 16: WDG_SW
0: Hardware watchdog
1: Software watchdog
Bits [15:8]: nRDP
Bits [7:0]: RDP: Read protection option byte
The value of this byte defines the Flash memory protection level
0xAA: Level 0
0xXX (except 0xAA and 0xCC): Level 1
0xCC: Level 2
The protection levels are stored in the Flash_OBR Flash option bytes register
(RDPRT bits).
Datax: Two bytes for user data storage.
These addresses can be programmed using the option byte programming
procedure.
Bits [31:24]: nData1
Bits [23:16]: Data1 (stored in FLASH_OBR[31:24])
Bits [15:8]: nData0
Bits [7:0]: Data0 (stored in FLASH_OBR[23:16])
DocID025202 Rev 7
Option bytes
Section 3.5 on page
RM0365
56.