Gpio Alternate Function Low Register (Gpiox_Afrl); (X = A; Gpio Alternate Function High Register (Gpiox_Afrh) - STMicroelectronics RM0365 Reference Manual

RM0365
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Bits 15:0 LCKy: Port x lock bit y (y= 0..15)
These bits are read/write but can only be written when the LCKK bit is '0.
10.4.9

GPIO alternate function low register (GPIOx_AFRL)

(x = A..H)
Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
AFR7[3:0]
rw rw rw
15 14 13
AFR3[3:0]
rw rw rw
Bits 31:0 AFRy[3:0]: Alternate function selection for port x pin y (y = 0..7)
These bits are written by software to configure alternate function I/Os
10.4.10

GPIO alternate function high register (GPIOx_AFRH)

(x = A..H)
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
AFR15[3:0]
rw rw rw
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
reset or peripheral reset.
LOCK key write sequence:
WR LCKR[16] = '1' + LCKR[15:0]
WR LCKR[16] = '0' + LCKR[15:0]
WR LCKR[16] = '1' + LCKR[15:0]
RD LCKR
RD LCKR[16] = '1' (this read operation is optional but it confirms that the lock is active)
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit will
return '1' until the next MCU reset or peripheral reset.
0: Port configuration not locked
1: Port configuration locked
28 27 26 25
AFR6[3:0]
rw rw rw rw
12 11 10 9
AFR2[3:0]
rw rw rw rw
28 27 26 25
AFR14[3:0]
rw rw rw rw
24 23 22
AFR5[3:0]
rw rw rw
8 7 6
AFR1[3:0]
rw rw rw
24 23 22
AFR13[3:0]
rw rw rw
DocID025202 Rev 7
General-purpose I/Os (GPIO)
21 20 19 18
AFR4[3:0]
rw rw rw rw
5 4 3 2
AFR0[3:0]
rw rw rw rw
21 20 19 18
AFR12[3:0]
rw rw rw rw
17 16
rw rw
1 0
rw rw
17 16
rw rw
168/1080
171