Syscfg Configuration Register 2 (Syscfg_Cfgr2) - STMicroelectronics RM0365 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

Some of the I/O pins mentioned in the above register may not be available on small

SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x18

System reset value: 0x0000

1. Available in STM32F302xB/xC/D/E only.

Bits 31:9 Reserved, must be kept at reset value

Bit 8 SRAM_PEF: SRAM parity error flag (STM32F302xB/C/D/E devices only)

This bit is set by hardware when an SRAM parity error is detected. It is cleared by

software by writing '1'.

0: No SRAM parity error detected

1: SRAM parity error detected

Bits 7:5 Reserved, must be kept at reset value

Bit 4 BYP_ADDR_PAR: Bypass address bit 29 in parity calculation

(STM32F302xB/C/D/E devices only)

This bit is set by software and cleared by a system reset. It is used to prevent an

unwanted parity error when the user writes a code in the RAM at address

0x2XXXXXXX (address in the address range 0x20000000-0x20002000) and then

executes the code from RAM at boot (RAM is remapped at address 0x00). In this

case, a read operation will be performed from the range 0x00000000-0x00002000

resulting in a parity error (the parity on the address is different).

0: The ramload operation is performed taking into consideration bit 29 of the

address when the parity is calculated.

1: The ramload operation is performed without taking into consideration bit 29 of

the address when the parity is calculated.

Bit 3 Reserved, must be kept at reset value

DocID025202 Rev 7

System configuration controller (SYSCFG)

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