Interconnection Details; Dma Interconnections; From Adc To Adc; From Adc To Tim - STMicroelectronics RM0365 Reference Manual

RM0365
Table 16. STM32F302xx peripherals interconnect matrix
1. X means interconnect, and "-" means no interconnect.
2. Only in STM32F302xB/C/D/E.
3. Only in STM32F302xD/E.
4. Not in STM32F302xB/C.
7.3

Interconnection details

7.3.1

DMA interconnections

Hardware DMA requests are managed by peripherals. The DMA channels dedicated to
each peripheral are summarized in
7.3.2

From ADC to ADC

ADC1 can be used as a "master" to trigger ADC2 "slave" start of conversion.
In dual ADC mode, the converted data of the master and slave ADCs can be read in
parallel.
A description of dual ADC mode is provided in
(STM32F302xB/C/D/E
7.3.3

From ADC to TIM

ADC1 can provide trigger event through watchdog signals to advanced-control timers
(TIM1).
A description of the ADC analog watchdog settings is provided in
window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH,
AWD_HTx, AWD_LTx,
The output (from ADC) is on signals ADC1_AWDx_OUT (x = 1..3 as there are 3 analog
watchdogs per ADC) and the input (to timer) on signal TIMx_ETR (external trigger).
TIMx_ETR is connected to ADC1_AWDx_OUT through bits in TIM1_OR registers; refer to
Section 20.4.21: TIM1 option registers
- - - - -
- - - - -
- - - - -
- - - - -
only).
AWDx).
Destination
- - - - -
- - - - -
- - - - -
- - - - -
Section 12.4.7: DMA request
Section 15.3.29: Dual ADC modes
(TIMx_OR).
DocID025202 Rev 7
Peripheral interconnect matrix
(1)
(continued)
- - x - -
- - x - -
- - x - -
- - x - -
mapping.
Section 15.3.28: Analog
- - - -
- - - -
- - - -
- - - -
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