Tim15 Registers; Tim15 Control Register 1 (Tim15_Cr1) - STMicroelectronics RM0365 Reference Manual

RM0365
22.5

TIM15 registers

Refer to
22.5.1

TIM15 control register 1 (TIM15_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 UIFREMAP: UIF status bit remapping
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (t
(TIx)
Bit 7 ARPE: Auto-reload preload enable
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
Section 2.1 for a list of abbreviations used in register descriptions.
12 11 10 9
UIF RE-
Res. CKD[1:0]
MAP
rw rw
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
00: t = t
DTS CK_INT
01: t = 2*t
DTS CK_INT
10: t = 4*t
DTS CK_INT
11: Reserved, do not program this value
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
General-purpose timers (TIM15/TIM16/TIM17)
8 7 6
ARPE Res.
rw rw
) used by the dead-time generators and the digital filters
DTS
DocID025202 Rev 7
5 4 3 2
Res. Res. OPM URS
rw rw
1 0
UDIS CEN
rw rw
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