Table 98. Adc Register Map And Reset Values (Master And Slave Adc Common Registers) Offset =0X300, X=1 Or 34) - STMicroelectronics RM0365 Reference Manual

RM0365
Table 98. ADC register map and reset values (master and slave ADC
Offset Register
ADCx_CSR
0x00
Reset value
0x04 Reserved
ADCx_CCR
0x08
Reset value
ADCx_CDR
0x0C
Reset value 0
Refer to
boundary addresses.
common registers) offset =0x300, x=1 or 34)
0 0 0
0 0
RDATA_SLV[15:0]
0 0 0 0 0 0 0 0
Section 3.2.2: Memory map and register boundary addresses
slave ADC2
0 0 0 0 0 0 0
Res.
0 0 0 0
0 0 0 0 0 0 0 0
DocID025202 Rev 7
Analog-to-digital converters (ADC)
master ADC1
0 0 0 0
DELAY[3:0]
0 0 0 0 0 0
RDATA_MST[15:0]
0 0 0 0 0 0 0 0 0
for the register
0 0 0 0 0 0
DUAL[4:0]
0 0 0 0 0
0 0 0 0 0 0
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