STMicroelectronics STM32F302xE Manuals

Manuals and User Guides for STMicroelectronics STM32F302xE. We have 1 STMicroelectronics STM32F302xE manual available for free PDF download: Reference Manual

STMicroelectronics STM32F302xE Reference Manual (1080 pages)

advanced ARM-based 32-bit MCUs

Brand: STMicroelectronics | Category: Computer Hardware | Size: 12 MB

Related Documents
1
Table of Contents
2
Overview of the Manual

40
- Table 1. Available Features Related to each Product
  40
Documentation Conventions

42
- List of Abbreviations for Registers
  42
- Glossary
  42
- Peripheral Availability
  42
System and Memory Overview

43
- System Architecture
  43
  - Figure 1. Stm32F302Xb/C System Architecture
    44
  - Figure 2. Stm32F302X6/8 System Architecture
    44
  - Figure 3. Stm32F302Xd/E System Architecture
    45
  - S0: I-Bus
    45
  - S1: D-Bus
    45
  - S2: S-Bus
    45
  - S3, S4: DMA-Bus
    45
  - Busmatrix
    46
- Memory Organization
  47
- Embedded SRAM
  55
  - Parity Check
    55
- Flash Memory Overview
  55
- Boot Configuration
  56
  - Embedded Boot Loader
    56
  - Table 5. Boot Modes
    56
Embedded Flash Memory

57
Option Byte Description

78
Cyclic Redundancy Check Calculation Unit (CRC)

81
- Introduction
  81
- CRC Main Features
  81
- CRC Functional Description
  82
- CRC Registers
  84
Peripheral Interconnect Matrix

87
- Introduction
  87
- Connection Summary
  87
- Table 16. Stm32F302Xx Peripherals Interconnect Matrix
  87
- Interconnection Details
  90
  - DMA Interconnections
    90
  - From ADC to ADC
    90
  - From ADC to TIM
    90
  - From TIM and EXTI to ADC
    91
  - From OPAMP to ADC
    91
  - From TS to ADC
    91
  - From VBAT to ADC
    91
  - Table 17. Vrefopampx to ADC Channel
    91
  - Table 18. OPAMP Output to ADC Input
    91
  - From VREFINT to ADC
    92
  - From COMP to TIM
    92
  - Table 19. Comparator Outputs to Timer Inputs
    92
  - From TIM to COMP
    93
  - From DAC to COMP
    93
  - Table 20. Timer Output Selection as Comparator Blanking Source
    93
  - From VREFINT to COMP
    94
  - From DAC to OPAMP
    94
  - From TIM to OPAMP
    94
  - From TIM to TIM
    94
  - From Break Input Sources to TIM
    95
  - From HSE, HSI, LSE, LSI, MCO, RTC to TIM
    95
  - Table 21. Timer Synchronization
    95
  - From TIM and EXTI to DAC
    96
  - From TIM to IRTIM
    96
  - Table 22. Timer and EXTI Signals Triggering DAC1 Conversions
    96
Power Control (PWR)

97
- Power Supplies
  97
- Power Supply Supervisor
  100
- Low-Power Modes
  102
  - Slowing down System Clocks
    102
  - Table 23. Low-Power Mode Summary
    102
  - Peripheral Clock Gating
    103
  - Sleep Mode
    103
  - Stop Mode
    104
  - Table 24. Sleep-Now
    104
  - Table 25. Sleep-On-Exit
    104
  - Standby Mode
    106
  - Table 26. Stop Mode
    106
  - Table 27. Standby Mode
    107
  - Auto-Wakeup from Low-Power Mode
    108
- Power Control Registers
  109
Reset and Clock Control (RCC)

113
- Reset
  113
  - Power Reset
    113
  - System Reset
    113
  - RTC Domain Reset
    114
  - Figure 11. Simplified Diagram of the Reset Circuit
    114
- Clocks
  115
  - Figure 12. Stm32F302Xb/C Clock Tree
    116
  - Figure 13. Stm32F302Xd/E Clock Tree
    117
  - Figure 14. Stm32F302X6/8 Clock Tree
    118
  - Figure 15. HSE/ LSE Clock Sources
    119
  - HSE Clock
    119
  - HSI Clock
    120
  - LSE Clock
    121
  - Pll
    121
  - Clock Security System (CSS)
    122
  - LSI Clock
    122
  - System Clock (SYSCLK) Selection
    122
  - ADC Clock
    123
  - RTC Clock
    123
  - Timers (Timx) Clock
    123
  - Clock-Out Capability
    124
  - I2S Clock
    124
  - Watchdog Clock
    124
  - Figure 16. Frequency Measurement with TIM16 in Capture Mode
    125
  - Internal/External Clock Measurement with TIM16
    125
- Low-Power Modes
  126
- RCC Registers
  127
General-Purpose I/Os (GPIO)

155
System Configuration Controller (SYSCFG)

172
- SYSCFG Registers
  172
Direct Memory Access Controller (DMA)

183
Interrupts and Events

205
Flexible Static Memory Controller (FSMC)

227
Analog-To-Digital Converters (ADC)

287
Digital-To-Analog Converter (DAC1)

393
Comparator (COMP)

407
- Introduction
  407
- COMP Main Features
  407
- COMP Functional Description
  408
- COMP Interrupts
  412
- COMP Registers
  413
Operational Amplifier (OPAMP)

423
Touch Sensing Controller (TSC)

437
Advanced-Control Timers (TIM1)

456
General-Purpose Timers (TIM2/TIM3/TIM4)

550
General-Purpose Timers (TIM15/TIM16/TIM17)

619
Basic Timers (TIM6)

693
Infrared Interface (IRTIM)

706
- Figure 279. IR Internal Hardware Connections with TIM16 and TIM17
  706
System Window Watchdog (WWDG)

707
- Introduction
  707
- WWDG Main Features
  707
- WWDG Functional Description
  707
  - Enabling the Watchdog
    708
  - Controlling the Downcounter
    708
  - Advanced Watchdog Interrupt Feature
    708
  - Figure 280. Watchdog Block Diagram
    708
  - How to Program the Watchdog Timeout
    709
  - Figure 281. Window Watchdog Timing Diagram
    709
  - Debug Mode
    710
- WWDG Registers
  710
  - Control Register (WWDG_CR)
    710
  - Configuration Register (WWDG_CFR)
    711
  - Status Register (WWDG_SR)
    711
  - WWDG Register Map
    712
  - Table 128. WWDG Register Map and Reset Values
    712
Independent Watchdog (IWDG)

713
- Introduction
  713
- IWDG Main Features
  713
- IWDG Functional Description
  713
  - IWDG Block Diagram
    713
  - Figure 282. Independent Watchdog Block Diagram
    713
  - Window Option
    714
  - Hardware Watchdog
    715
  - Behavior in Stop and Standby Modes
    715
  - Register Access Protection
    715
  - Debug Mode
    715
- IWDG Registers
  716
  - Key Register (IWDG_KR)
    716
  - Prescaler Register (IWDG_PR)
    717
  - Reload Register (IWDG_RLR)
    718
  - Status Register (IWDG_SR)
    719
  - Window Register (IWDG_WINR)
    720
  - IWDG Register Map
    721
  - Table 129. IWDG Register Map and Reset Values
    721
Real-Time Clock (RTC)

722
- Introduction
  722
- RTC Main Features
  723
- RTC Functional Description
  724
  - RTC Block Diagram
    724
  - Figure 283. RTC Block Diagram
    724
  - Gpios Controlled by the RTC
    725
  - Table 130. RTC Pin PC13 Configuration
    726
  - Table 131. LSE Pin PC14 Configuration
    726
  - Table 132. LSE Pin PC15 Configuration
    726
  - Clock and Prescalers
    727
  - Real-Time Clock and Calendar
    727
  - Programmable Alarms
    728
  - Periodic Auto-Wakeup
    728
  - RTC Initialization and Configuration
    729
  - Reading the Calendar
    730
  - Resetting the RTC
    731
  - RTC Synchronization
    732
  - RTC Reference Clock Detection
    732
  - RTC Smooth Digital Calibration
    733
  - Time-Stamp Function
    735
  - Tamper Detection
    736
  - Calibration Clock Output
    737
  - Alarm Output
    738
- RTC Low-Power Modes
  738
- RTC Interrupts
  738
- Table 133. Effect of Low-Power Modes on RTC
  738
- RTC Registers
  739
Inter-Integrated Circuit (I2C) Interface

765
Universal Synchronous Asynchronous Receiver

835
Transmitter (USART)

835
Serial Peripheral Interface / Inter-IC Sound (SPI/I2S)

902
Controller Area Network (Bxcan)

960
- Introduction
  960
- Bxcan Main Features
  960
- Bxcan General Description
  961
  - CAN 2.0B Active Core
    961
  - Control, Status and Configuration Registers
    961
  - Tx Mailboxes
    961
  - Figure 378. CAN Network Topology
    961
  - Acceptance Filters
    962
- Bxcan Operating Modes
  962
  - Initialization Mode
    962
  - Normal Mode
    962
  - Sleep Mode (Low-Power)
    963
- Test Mode
  964
  - Silent Mode
    964
  - Figure 379. Bxcan Operating Modes
    964
  - Loop Back Mode
    965
  - Loop Back Combined with Silent Mode
    965
  - Figure 380. Bxcan in Silent Mode
    965
  - Figure 381. Bxcan in Loop Back Mode
    965
- Behavior in Debug Mode
  966
- Bxcan Functional Description
  966
  - Transmission Handling
    966
  - Figure 382. Bxcan in Combined Mode
    966
  - Time Triggered Communication Mode
    967
  - Figure 383. Transmit Mailbox States
    967
  - Reception Handling
    968
  - Figure 384. Receive FIFO States
    968
  - Identifier Filtering
    969
  - Figure 385. Filter Bank Scale Configuration - Register Organization
    971
  - Figure 386. Example of Filter Numbering
    972
  - Message Storage
    973
  - Figure 387. Filtering Mechanism - Example
    973
  - Table 167. Transmit Mailbox Mapping
    974
  - Table 168. Receive Mailbox Mapping
    974
  - Figure 388. CAN Error State Diagram
    974
  - Error Management
    975
  - Bit Timing
    975
  - Figure 389. Bit Timing
    976
  - Figure 390. CAN Frames
    977
- Bxcan Interrupts
  978
- Figure 391. Event Flags and Interrupt Generation
  978
- CAN Registers
  979
  - Register Access Protection
    979
  - CAN Control and Status Registers
    979
  - CAN Mailbox Registers
    989
  - Figure 392. Can Mailbox Registers
    990
  - CAN Filter Registers
    996
  - Bxcan Register Map
    1000
  - Table 169. Bxcan Register Map and Reset Values
    1000
Universal Serial Bus Full-Speed Device Interface (USB)

1004
- Introduction
  1004
- USB Main Features
  1004
- USB Implementation
  1004
- Table 170. Stm32F302Xx USB Implementation
  1004
- USB Functional Description
  1005
  - Figure 393. USB Peripheral Block Diagram
    1005
  - Description of USB Blocks
    1006
- Programming Considerations
  1007
  - Generic USB Device Programming
    1008
  - System and Power-On Reset
    1008
  - Figure 394. Packet Buffer Areas with Examples of Buffer Description Table Locations
    1010
  - Control Transfers
    1012
  - Double-Buffered Endpoints
    1013
  - Table 171. Double-Buffering Buffer Flag Definition
    1014
  - Table 172. Bulk Double-Buffering Memory Buffers Usage
    1014
  - Isochronous Transfers
    1015
  - Table 173. Isochronous Memory Buffers Usage
    1016
  - Suspend/Resume Events
    1017
  - Table 174. Resume Event Detection
    1018
- USB Registers
  1019
  - Common Registers
    1019
  - Table 175. Reception Status Encoding
    1029
  - Table 176. Endpoint Type Encoding
    1030
  - Table 177. Endpoint Kind Meaning
    1030
  - Table 178. Transmission Status Encoding
    1030
  - Buffer Descriptor Table
    1031
  - Table 179. Definition of Allocated Buffer Memory
    1033
  - USB Register Map
    1035
  - Table 180. USB Register Map and Reset Values
    1035
Debug Support (DBG)

1037
- Overview
  1037
- Figure 395. Block Diagram of STM32 MCU and Cortex-M4
  1037
- Reference ARM® Documentation
  1038
- SWJ Debug Port (Serial Wire and JTAG)
  1038
  - Mechanism to Select the JTAG-DP or the SW-DP
    1039
- Pinout and Debug Port Pins
  1039
  - Figure 396. SWJ Debug Port
    1039
  - Flexible SWJ-DP Pin Assignment
    1040
  - SWJ Debug Port Pins
    1040
  - Table 181. SWJ Debug Port Pins
    1040
  - Table 182. Flexible SWJ-DP Pin Assignment
    1040
  - Internal Pull-Up and Pull-Down on JTAG Pins
    1041
  - Using Serial Wire and Releasing the Unused Debug Pins as Gpios
    1042
- Stm32F302Xx JTAG TAP Connection
  1042
- ID Codes and Locking Mechanism
  1043
  - Figure 397. JTAG TAP Connections
    1043
  - Boundary Scan TAP
    1044
  - Cortex-M4 ® F TAP
    1044
  - MCU Device ID Code
    1044
  - Cortex-M4
    1045
- JTAG Debug Port
  1045
- Table 183. JTAG Debug Port Data Registers
  1045
- Table 184. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
  1046
- SW Debug Port
  1047
  - SW Protocol Introduction
    1047
  - SW Protocol Sequence
    1047
  - Table 185. Packet Request (8-Bits)
    1047
  - SW-DP State Machine (Reset, Idle States, ID Code)
    1048
  - DP and AP Read/Write Accesses
    1048
  - Table 186. ACK Response (3 Bits)
    1048
  - Table 187. DATA Transfer (33 Bits)
    1048
  - SW-DP Registers
    1049
  - Table 188. SW-DP Registers
    1049
  - SW-AP Registers
    1050
- AHB-AP (AHB Access Port) - Valid for both JTAG-DP and SW-DP
  1050
- Table 189. Cortex-M4 ® F AHB-AP Registers
  1050
- Core Debug
  1051
- Capability of the Debugger Host to Connect under System Reset
  1051
- Table 190. Core Debug Registers
  1051
- FPB (Flash Patch Breakpoint)
  1052
- DWT (Data Watchpoint Trigger)
  1053
- MCU Debug Component (DBGMCU)
  1053
  - Debug Support for Low-Power Modes
    1053
  - Debug Support for Timers, Watchdog, Bxcan and I
    1054
  - 1054
    1054
  - Debug MCU Configuration Register
    1054
  - Debug MCU APB1 Freeze Register (DBGMCU_APB1_FZ)
    1056
  - Debug MCU APB2 Freeze Register (DBGMCU_APB2_FZ)
    1058
- TPIU (Trace Port Interface Unit)
  1058
  - Introduction
    1058
  - TRACE Pin Assignment
    1059
  - Table 191. Asynchronous TRACE Pin Assignment
    1059
  - Table 192. Synchronous TRACE Pin Assignment
    1059
  - Figure 398. TPIU Block Diagram
    1059
  - Table 193. Flexible TRACE Pin Assignment
    1060
  - TPUI Formatter
    1061
  - TPUI Frame Synchronization Packets
    1061
    
    Transmission of the Synchronization Frame Packet
    1062
    
    Synchronous Mode
    1062
    
    Asynchronous Mode
    1062
    
    TRACECLKIN Connection Inside the Stm32F302Xx
    1063
    
    TPIU Registers
    1064
    
    Table 194. Important TPIU Registers
    1064
    
    33.15.10 Example of Configuration
    1065
  - DBG Register Map
    1066
  - Table 195. DBG Register Map and Reset Values
    1066
Device Electronic Signature

1067
- Unique Device ID Register (96 Bits)
  1067
- Memory Size Data Register
  1068
  - Flash Size Data Register
    1068
Revision History

1072
- Table 196. Document Revision History
  1072

STMicroelectronics Categories

Motherboard Microcontrollers Computer Hardware Controller Control Unit

More STMicroelectronics Manuals

STMicroelectronics STM32F302xE Manuals

STMicroelectronics STM32F302xE Reference Manual (1080 pages)

Table of Contents

Overview of the Manual

Documentation Conventions

System and Memory Overview

Embedded Flash Memory

Option Byte Description

Cyclic Redundancy Check Calculation Unit (CRC)

Peripheral Interconnect Matrix

Power Control (PWR)

Reset and Clock Control (RCC)

General-Purpose I/Os (GPIO)

System Configuration Controller (SYSCFG)

Direct Memory Access Controller (DMA)

Interrupts and Events

Flexible Static Memory Controller (FSMC)

Analog-To-Digital Converters (ADC)

Digital-To-Analog Converter (DAC1)

Comparator (COMP)

Operational Amplifier (OPAMP)

Touch Sensing Controller (TSC)

Advanced-Control Timers (TIM1)

General-Purpose Timers (TIM2/TIM3/TIM4)

General-Purpose Timers (TIM15/TIM16/TIM17)

Basic Timers (TIM6)

Infrared Interface (IRTIM)

System Window Watchdog (WWDG)

Independent Watchdog (IWDG)

Real-Time Clock (RTC)

Inter-Integrated Circuit (I2C) Interface

Universal Synchronous Asynchronous Receiver

Transmitter (USART)

Serial Peripheral Interface / Inter-IC Sound (SPI/I2S)

Controller Area Network (Bxcan)

Universal Serial Bus Full-Speed Device Interface (USB)

Debug Support (DBG)

Device Electronic Signature

Revision History

Related Products

STMicroelectronics Categories