Figure 353. Master Full-Duplex Communication In Packed Mode - STMicroelectronics RM0365 Reference Manual

RM0365

Figure 353. Master full-duplex communication in packed mode

Assumptions for master full-duplex communication in packed mode example:
• Data size = 5 bit
•
Read/write FIFO is performed mostly by 16-bit access
• FRXTH=0
If DMA is used:
•
Number of Tx frames to be transacted by DMA is set to 3
•
Number of Rx frames to be transacted by DMA is set to 3
•
PSIZE for both Tx and Rx DMA channel is set to 16-bit
•
LDMA_TX=1 and LDMA_RX=1
See also
and notes.
: Communication diagrams on page 918
DocID025202 Rev 7
Serial peripheral interface / inter-IC sound (SPI/I2S)
for details about common assumptions
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