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Touch sensing controller (TSC)
19.6.3
TSC interrupt clear register (TSC_ICR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 MCEIC: Max count error interrupt clear
This bit is set by software to clear the max count error flag and it is cleared by hardware when
the flag is reset. Writing a '0' has no effect.
Bit 0 EOAIC: End of acquisition interrupt clear
This bit is set by software to clear the end of acquisition flag and it is cleared by hardware
when the flag is reset. Writing a '0' has no effect.
449/1080
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
0: No effect
1: Clears the corresponding MCEF of the TSC_ISR register
0: No effect
1: Clears the corresponding EOAF of the TSC_ISR register
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
DocID025202 Rev 7
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0365
17
16
Res.
Res.
1
0
MCEIC EOAIC
rw
rw
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