STMicroelectronics RM0365 Reference Manual page 33

List of figures
Figure 51. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 52. ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 53. ADC1 and ADC2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Figure 54. ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Figure 55. Updating the ADC calibration factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 56. Mixing single-ended and differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 57. Enabling / Disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 58. Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Figure 59. Stopping ongoing regular conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 60. Stopping ongoing regular and injected conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 61. Triggers are shared between ADC master & ADC slave . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 62. Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 63. Example of JSQR queue of context (sequence change) . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 64. Example of JSQR queue of context (trigger change) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 65. Example of JSQR queue of context with overflow before conversion . . . . . . . . . . . . . . . 314
Figure 66. Example of JSQR queue of context with overflow during conversion . . . . . . . . . . . . . . . 314
Figure 67. Example of JSQR queue of context with empty queue (case JQM=0). . . . . . . . . . . . . . . 315
Figure 68. Example of JSQR queue of context with empty queue (case JQM=1). . . . . . . . . . . . . . . 315
Figure 69. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . . . . . . . . . . . . . . . . . . . . 316
Figure 70. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 71. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . 317
Figure 72. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . . . . . . . . . . . . . . 317
Figure 73. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . . . . . . . . . . . . . . . . . 318
Figure 74. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . . . . . . . . . . . . . . . . . 318
Figure 75. Example of JSQR queue of context when changing SW and HW triggers. . . . . . . . . . . . 319
Figure 76. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 77. Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 78. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 79. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 80. Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 81. Right alignment (offset enabled, signed value). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 82. Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 83. Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 84. Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 85. AUTODLY=1, regular conversion in continuous mode, software trigger . . . . . . . . . . . . . 329
Figure 86. AUTODLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Figure 87. AUTODLY=1, regular HW conversions interrupted by injected conversions . . . . . . . . . . . . .
(DISCEN=1, JDISCEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Figure 88. AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . 332
Figure 89. AUTODLY=1 in auto- injected mode (JAUTO=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 90. Analog watchdog's guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Figure 91. ADCy_AWDx_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . . 335
Figure 92. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) . . . . . . . . . . . . . . 336
Figure 93. ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . . 336
Figure 94. ADCy_AWDx_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . . 336
Figure 95. Dual ADC block diagram
Figure 96. Injected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 339
33/1080
(1)
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