STMicroelectronics RM0365 Reference Manual page 133

Reset and clock control (RCC)
Bit 11 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
Bit 10 HSIRDYIE: HSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI oscillator
stabilization.
Bit 9 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization.
Bit 8 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator
stabilization.
Bit 7 CSSF: Clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
Bit 3 HSERDYF: HSE ready interrupt flag
Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
133/1080
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
DocID025202 Rev 7
RM0365