Figure 86. Autodly=1, Regular Hw Conversions Interrupted By Injected Conversions (Discen=0; Jdiscen=0); Figure 87. Autodly=1, Regular Hw Conversions Interrupted By Injected Conversions - STMicroelectronics RM0365 Reference Manual

RM0365 Analog-to-digital converters (ADC)
Figure 86. AUTODLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0)
1. AUTDLY=1
2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6
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