Analog-to-digital converters (ADC)
Figure 75. Example of JSQR queue of context when changing SW and HW triggers
1. Parameters:
P1: sequence of 1 conversion, hardware trigger (JEXTEN /=0x0)
P2: sequence of 1 conversion, hardware trigger (JEXTEN /= 0x0)
P3: sequence of 1 conversion, software trigger (JEXTEN = 0x0)
P4: sequence of 1 conversion, hardware trigger (JEXTEN /= 0x0)
Queue of context: Starting the ADC with an empty queue
The following procedure must be followed to start ADC operation with an empty queue, in
case the first context is not known at the time the ADC is initialized. This procedure is only
applicable when JQM bit is reset:
5.
Write a dummy JSQR with JEXTEN not equal to 0 (otherwise triggering a software
conversion)
6.
Set JADSTART
7.
Set JADSTP
8.
Wait until JADSTART is reset
9.
Set JADSTART.
15.3.22
Programmable resolution (RES) - fast conversion mode
It is possible to perform faster conversion by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the control
bits RES[1:0].
format with respect to the resolution as well as to the data alignment.
Lower resolution allows faster conversion time for applications where high-data precision is
not required. It reduces the conversion time spent by the successive approximation steps
according to
319/1080
Figure
80,
Figure
81,
Table
89.
DocID025202 Rev 7
Figure 82
and
Figure 83
show the conversion result
RM0365
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