Dma Features; I 2 S Interrupts; Table 165. I - STMicroelectronics RM0365 Reference Manual

RM0365
Frame error flag (FRE)
This flag can be set by hardware only if the I
external master is changing the WS line while the slave is not expecting this change. If the
synchronization is lost, the following steps are required to recover from this state and
resynchronize the external master device with the I
1. Disable the I
2. Enable it again when the correct level is detected on the WS line (WS line is high in I
mode or low for MSB- or LSB-justified or PCM modes.
Desynchronization between master and slave devices may be due to noisy environment on
the CK communication clock or on the WS frame synchronization line. An error interrupt can
be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by
software when the status register is read.
30.7.10

DMA features

2
In I S mode, the DMA works in exactly the same way as it does in SPI mode. There is no
difference except that the CRC feature is not available in I
transfer protection system.
2
30.8 I S interrupts
Table 165
Transmit buffer empty flag
Receive buffer not empty flag
Overrun error
Underrun error
Frame error flag
2
S.
2
provides the list of I S interrupts.

Table 165. I

Interrupt event
DocID025202 Rev 7
Serial peripheral interface / inter-IC sound (SPI/I2S)
2
S is configured in Slave mode. It is set if the
2
S slave device:
2
2
S interrupt requests
Event flag
TXE
RXNE
OVR
UDR
FRE
S mode since there is no data
Enable control bit
TXEIE
RXNEIE
ERRIE
2
S
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