RM0365
Table 87
injected conversion.
Table 87. ADC1 (master) & 2 (slave) - External triggers for regular channels
Name
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
EXT8
EXT9
EXT10
EXT11
EXT12
EXT13
EXT14
EXT15
Table 88. ADC1 & ADC2 - External trigger for injected channels
Name
JEXT0
JEXT1
JEXT2
JEXT3
JEXT4
JEXT5
JEXT6
JEXT7
JEXT8
JEXT9
JEXT10
JEXT11
JEXT12
to
Table 88
give all the possible external triggers of the two ADCs for regular and
Source
TIM1_CC1 event
TIM1_CC2 event
TIM1_CC3 event
TIM2_CC2 event
TIM3_TRGO event
TIM4_CC4 event
EXTI line 11
Reserved
Reserved
TIM1_TRGO event
TIM1_TRGO2 event
TIM2_TRGO event
TIM4_TRGO event
TIM6_TRGO event
TIM15_TRGO event
TIM3_CC4 event
Source
TIM1_TRGO event
TIM1_CC4 event
TIM2_TRGO event
TIM2_CC1 event
TIM3_CC4 event
TIM4_TRGO event
EXTI line 15
Reserved
TIM1_TRGO2 event
Reserved
Reserved
TIM3_CC3 event
TIM3_TRGO event
DocID025202 Rev 7
Analog-to-digital converters (ADC)
Type
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
External pin
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
Type
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
External pin
-
Internal signal from on chip timers
Internal signal from on chip timers
Internal signal from on chip timers
EXTSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
JEXTSEL[3..0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
308/1080
392
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